Managing frequency changes of clock signals across different clock domains
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United States of America Patent
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Jan 1, 2019
Grant Date -
Jan 18, 2018
app pub date -
Jul 13, 2016
filing date -
Jul 13, 2016
priority date (Note) -
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Abstract
A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.
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