Deterministic calibrated synchronized network interlink access

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United States of America Patent

PATENT NO 10764027
APP PUB NO 20180013541A1
SERIAL NO

15204937

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Abstract

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Technologies for calibrated network interlink access. In some embodiments, a system can calculate a first communication latency of a first link between a first processing element in a first switch and a second processing element in a second switch, and a second communication latency associated with a second link between the first processing element and a third processing element in a third switch. The system can determine a delta between the first communication latency and the second communication latency, and whether respective clock rates of the first switch, second switch, and third switch have a clock rate variation, to yield a clock rate variation determination. Based on the delta and clock rate variation determination, the system can determine an offset value for synchronizing the first communication latency and second communication latency. Based on the offset value, the system can calibrate traffic over the first link and/or the second link.

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Patent Owner(s)

Patent OwnerAddress
CISCO TECHNOLOGY INC170 WEST TASMAN DRIVE SAN JOSE CA 95134

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Kelvin San Jose, US 130 2636
Huang, Chih-Tsung San Jose, US 63 565
Huang, Wei-Jen San Jose, US 89 1321
Swarnamanjunathan, Keerthi Manjunathan San Jose, US 10 45

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