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Abstract

A data processing device includes: a FIFO buffer; a write circuit writing data in the buffer according to a write clock signal; a read circuit reading data from the buffer according to a read clock signal, a PLL circuit conducting a phase synchronization processing of the read clock signal based on a phase difference between the write and read clock signals and outputting a notification signal when the phase difference becomes within a predetermined range; a write control circuit controlling a timing when the write circuit starts writing based on the notification signal; a read control circuit comparing an address in which data is written and a reference address and controlling a timing when the read circuit starts reading based on a comparison result; and a correction circuit correcting the reference address with a value corresponding to the phase difference obtained when the notification signal has been output.

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First Claim