I/O cell
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United States of America Patent
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Aug 7, 2018
Grant Date -
Jan 11, 2018
app pub date -
Jun 29, 2017
filing date -
Jul 11, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
An I/O cell includes a reference output circuit that has a reference output transistor, connected to an output terminal, and has a reference pre-buffer, the reference pre-buffer driving the reference output transistor according to an input signal of the input terminal; adjustment output circuits that have an adjustment output transistor, connected to the output terminal and connected in parallel with the reference output transistor, and have an adjustment pre-buffer, the adjustment pre-buffer driving the adjustment output transistor according to the input signal; and a gate voltage detection control circuit that monitors all of gate voltages applied to the output transistors included in the reference output circuit and the adjustment output circuit. The gate voltage detection control circuit generates a timing when all of the output transistors are turned OFF when switching the H/L level of the output current to the load according to the change of the input signal.
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