Gate length controlled vertical FETs
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 11, 2018
Grant Date -
Jan 11, 2018
app pub date -
Jul 11, 2016
filing date -
Jul 11, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second type on a substrate of a first type, growing a channel layer on the bottom source-drain layer, forming a first fin from the channel layer with mask on top of the first fin. A width of the mask is wider than a final first fin width.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully