Fabrication of a vertical fin field effect transistor with a reduced contact resistance
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United States of America Patent
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Mar 19, 2019
Grant Date -
Jan 11, 2018
app pub date -
Sep 5, 2017
filing date -
Jun 24, 2016
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Abstract
A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.
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