Field-effect transistors having contacts to 2D material active region
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United States of America Patent
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May 7, 2019
Grant Date -
Jan 11, 2018
app pub date -
Jul 6, 2016
filing date -
Jul 6, 2016
priority date (Note) -
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Abstract
Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
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