Three-dimensional semiconductor memory devices
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United States of America Patent
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Aug 20, 2019
Grant Date -
Jan 11, 2018
app pub date -
May 4, 2017
filing date -
Jul 6, 2016
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Abstract
A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.
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