Semiconductor device including barrier pattern and metal pattern
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United States of America Patent
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Dec 25, 2018
Grant Date -
Jan 11, 2018
app pub date -
Sep 7, 2017
filing date -
Mar 29, 2016
priority date (Note) -
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Abstract
The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.
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