Semiconductor device and method of manufacturing the same

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United States of America Patent

PATENT NO 9985043
SERIAL NO

15498547

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Abstract

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An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO

International Classification(s)

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  • 2017 Application Filing Year
  • H01L Class
  • 30754 Applications Filed
  • 25260 Patents Issued To-Date
  • 82.14 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tsuda, Shibun Tokyo, JP 15 29

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Patent Citation Ranking

  • 1 Citation Count
  • H01L Class
  • 23.71 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3689997611243481558461392216162801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500900095001000010500

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