Integrated circuits
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United States of America Patent
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Mar 5, 2019
Grant Date -
Jan 11, 2018
app pub date -
Jan 29, 2015
filing date -
Jan 29, 2015
priority date (Note) -
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Abstract
The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.
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