Anti-fuse with reduced programming voltage
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United States of America Patent
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Mar 5, 2019
Grant Date -
Jan 11, 2018
app pub date -
Sep 1, 2017
filing date -
Jun 6, 2016
priority date (Note) -
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Abstract
A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
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