Stable and reliable FinFET SRAM with improved beta ratio
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United States of America Patent
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Jul 30, 2019
Grant Date -
Jan 11, 2018
app pub date -
Sep 14, 2017
filing date -
May 11, 2016
priority date (Note) -
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Abstract
Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.
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