SOI wafers with buried dielectric layers to prevent CU diffusion
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United States of America Patent
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Mar 26, 2019
Grant Date -
Jan 11, 2018
app pub date -
Sep 25, 2017
filing date -
Dec 29, 2015
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Abstract
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.
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