Semiconductor memory device
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United States of America Patent
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Jun 11, 2019
Grant Date -
Jan 11, 2018
app pub date -
Jan 4, 2017
filing date -
Jul 11, 2016
priority date (Note) -
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Abstract
Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.
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