Power saving method and apparatus for first in first out (FIFO) memories
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United States of America Patent
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Mar 26, 2019
Grant Date -
Jan 11, 2018
app pub date -
Jul 17, 2017
filing date -
Nov 30, 2011
priority date (Note) -
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Abstract
In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.
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