Method and Apparatus for Shared Virtual Memory to Manage Data Coherency in a Heterogeneous Processing System
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United States of America Patent
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Jul 6, 2016
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Jul 6, 2016
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One embodiment provides for a heterogeneous computing device comprising a first processor coupled with a second processor, wherein one or more of the first or second processor includes graphics processing logic; wherein each of the first processor and the second processor includes first logic to perform virtual to physical memory address translation; and wherein the first logic includes cache coherency state for a block of memory associated with a virtual memory address.
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