Using data pattern to mark cache lines as invalid
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United States of America Patent
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Jan 8, 2019
Grant Date -
Jan 11, 2018
app pub date -
Jul 11, 2016
filing date -
Jul 11, 2016
priority date (Note) -
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Abstract
An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.
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