Apparatus to optimize GPU thread shared local memory access
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United States of America Patent
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Oct 2, 2018
Grant Date -
Jan 11, 2018
app pub date -
Jul 7, 2016
filing date -
Jul 7, 2016
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Abstract
One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.
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