Restricted address translation to protect against device-TLB vulnerabilities
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United States of America Patent
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Aug 14, 2018
Grant Date -
Jan 11, 2018
app pub date -
Jul 11, 2016
filing date -
Jul 11, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.
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