Memory system and operating method thereof
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United States of America Patent
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Aug 20, 2019
Grant Date -
Jan 11, 2018
app pub date -
Dec 1, 2016
filing date -
Jul 8, 2016
priority date (Note) -
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Abstract
A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.
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