INTEGRATED CIRCUITS WITH HYBRID FIXED/CONFIGURABLE CLOCK NETWORKS
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United States of America Patent
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Issued Date -
Jan 4, 2018
app pub date -
Jun 29, 2016
filing date -
Jun 29, 2016
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Abstract
An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. Both the configurable clock routing paths and the fixed clock routing paths can be implemented using an array of logic regions, where each logic region includes a clock switching box, a horizontal routing segment, a vertical routing segment, and associated logic circuitry. The configurable routing paths may include horizontal/vertical routing segments with bidirectional tristate buffers. The fixed routing paths may include horizontal/vertical routing segments with unidirectional inverters that are configured to form an H-tree.
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