MEMS TRANSDUCER PACKAGE
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United States of America Patent
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Issued Date -
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app pub date -
Dec 4, 2015
filing date -
Dec 23, 2014
priority date (Note) -
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Abstract
A method of fabricating a micro-electrical-mechanical system (MEMS) transducer chip scale package. The method comprising: providing (101) a front side pre-fabricated semiconductor die wafer (1) comprising a plurality of individual die that each comprise at least a MEMS transducer. And back etching (104) the semiconductor die wafer (1) at the back side (4) of the semiconductor die wafer (1) by etching an acoustic die channel (5) through each respective die of the plurality of die and etching a die back volume (6) into each respective die of the plurality of die. The semiconductor die wafer (1) is capped with a cap wafer (16) such that a wafer level packaged MEMS transducer wafer is provided containing multiple MEMS transducer chip scale packages.
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD | 7B NIGHTINGALE WAY QUARTERMILE EDINBURGH EH3 9EG |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
HOEKSTRA, Tsjerk | Balerno, GB | 12 | 87 |
# of filed Patents : 12 Total Citations : 87 | |||
PATTEN, David Talmage | Austin, US | 4 | 30 |
# of filed Patents : 4 Total Citations : 30 |
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- 1 Citation Count
- H04R Class
- 20.74 % this patent is cited more than
- 8 Age
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