AES Hardware Implementation
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United States of America Patent
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Jun 27, 2017
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Jun 28, 2016
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Abstract
A method of performing at least one of end-to-end Advanced Encryption Standard (AES) encryption and end-to-end AES decryption in an instruction execution module comprising hardware logic in a processor having an instruction set, receives in response to a particular instruction set being executed, key values and text data identified by operands in the executed instruction, the received key values defining an initial round key and forming current key values and the received text data defining an initial state array to be processed in an initial round and forming a current state array; and for each round of a plurality of rounds of
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