Frequency based bias voltage scaling for phase locked loops
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 12, 2020
Grant Date -
Dec 28, 2017
app pub date -
Jun 28, 2016
filing date -
Jun 28, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
INTEL CORPORATION | 2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054 |
International Classification(s)

- 2016 Application Filing Year
- H03L Class
- 676 Applications Filed
- 589 Patents Issued To-Date
- 87.14 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Dietl-Steinmaurer, Herwig | Wels, AT | 3 | 25 |
# of filed Patents : 3 Total Citations : 25 | |||
Gustedt, Thomas | Munich, DE | 4 | 13 |
# of filed Patents : 4 Total Citations : 13 | |||
Roithmeier, Andreas | Munich, DE | 10 | 54 |
# of filed Patents : 10 Total Citations : 54 | |||
Wicpalek, Christian | Puchenau, AT | 19 | 113 |
# of filed Patents : 19 Total Citations : 113 |
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Patent Citation Ranking
- 1 Citation Count
- H03L Class
- 34.27 % this patent is cited more than
- 5 Age
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