Frequency based bias voltage scaling for phase locked loops

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United States of America Patent

PATENT NO 10651857
APP PUB NO 20170373694A1
SERIAL NO

15194999

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Abstract

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A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.

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Patent Owner(s)

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INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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  • 2016 Application Filing Year
  • H03L Class
  • 676 Applications Filed
  • 589 Patents Issued To-Date
  • 87.14 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2016201720182019202020210255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dietl-Steinmaurer, Herwig Wels, AT 3 25
Gustedt, Thomas Munich, DE 4 13
Roithmeier, Andreas Munich, DE 10 54
Wicpalek, Christian Puchenau, AT 19 113

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  • 1 Citation Count
  • H03L Class
  • 34.27 % this patent is cited more than
  • 5 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges25748093101 - 1011 - 2021 - 3031 - 400255075100125150175200225250275300325350375400425450475500525

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