Wafer level chip scale semiconductor package
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United States of America Patent
Stats
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Oct 23, 2018
Grant Date -
Dec 28, 2017
app pub date -
Feb 13, 2017
filing date -
Jun 23, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
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- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Apr 23, 2026 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Apr 23, 2030 |
