Stacked silicon package assembly having conformal lid
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United States of America Patent
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Mar 19, 2019
Grant Date -
Dec 28, 2017
app pub date -
Jun 24, 2016
filing date -
Jun 24, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.
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