Test of stacked transistors

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United States of America Patent

PATENT NO 10884050
APP PUB NO 20170363676A1
SERIAL NO

15188788

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Abstract

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A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.

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PSEMI CORPORATION9369 CARROLL PARK DRIVE SAN DIEGO CA 92121

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  • 2016 Application Filing Year
  • H03K Class
  • 2511 Applications Filed
  • 2079 Patents Issued To-Date
  • 82.80 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances201620172018201920202021202220230255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shapiro, Eric S San Diego, US 44 274

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges14751179187101 - 1011 - 2021 - 3051 - 6001002003004005006007008009001000110012001300140015001600

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