Semiconductor heterostructure with at least one stress control layer
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United States of America Patent
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Feb 16, 2021
Grant Date -
Dec 7, 2017
app pub date -
May 23, 2017
filing date -
Jun 1, 2016
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Abstract
A semiconductor heterostructure for an optoelectronic device is disclosed. The semiconductor heterostructure includes at least one stress control layer within a plurality of semiconductor layers used in the optoelectronic device. Each stress control layer includes stress control regions separated from adjacent stress control regions by a predetermined spacing. The stress control layer induces one of a tensile stress and a compressive stress in an adjacent semiconductor layer.
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