Memory and method for operating a memory with interruptible command sequence
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United States of America Patent
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May 14, 2019
Grant Date -
Dec 7, 2017
app pub date -
Jan 20, 2017
filing date -
Jun 7, 2016
priority date (Note) -
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Abstract
A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.
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