MOS transistor for radiation-tolerant digital CMOS circuits
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United States of America Patent
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May 19, 2020
Grant Date -
Nov 23, 2017
app pub date -
May 8, 2017
filing date -
May 19, 2016
priority date (Note) -
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Abstract
A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well region, comprising doped source and drain regions of a second conductivity type and at least one MOS channel region extending between the source and drain regions under a respective gate stack, and a dielectric isolation layer of the STI or LOCOS type and laterally surrounding same, wherein well portions of the well region adjoin the MOS channel region in the two opposite longitudinal directions oriented perpendicular to a notional connecting line extending from the source through the MOS channel region to the drain region, and which extend as far as a surface of the active MOS transistor region, so that the respective well portion adjoining the MOS channel region is arranged between the MOS channel region and the dielectric isolation layer.
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