CTE compensation for wafer-level and chip-scale packages and assemblies

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10847469
APP PUB NO 20170330836A1
SERIAL NO

15651531

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Abstract

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A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.

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Patent Owner(s)

Patent OwnerAddress
CUBIC CORPORATION9333 BALBOA AVENUE SAN DIEGO CA 92123

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beroz, Masud Apex, US 103 3246
Boryssenko, Anatoliy O Belchertown, US 7 76
Caba, Aaron C Blacksburg, US 2 11
Huettner, Steven E Tucson, US 11 106
Jordan, Jared W Raleigh, US 6 131
Smith, Timothy A Durham, US 8 139
Vanhille, Kenneth J Cary, US 2 97

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