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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
ROCHESTER INSTITUTE OF TECHNOLOGY	145 LOMB MEMORIAL DRIVE ROCHESTER NY 14623-5603

International Classification(s)

• H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

• 2017 Application Filing Year
• H01L Class
• 30754 Applications Filed
• 25260 Patents Issued To-Date
• 82.14 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Ganguly, Amlan	Rochester, US	3	5
# of filed Patents : 3 Total Citations : 5
Kandlikar, Satish G	Rochester, US	21	77
# of filed Patents : 21 Total Citations : 77

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Patent Citation Ranking

• 2 Citation Count
• H01L Class

• 18.50 % this patent is cited more than
• 8 Age

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Full Text

US Patent Application No: 2015/0035,044

Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability

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Abstract

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A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

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Description

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