MOS TRANSISTOR STRUCTURE, IN PARTICULAR FOR HIGH VOLTAGES USING A TECHNOLOGY OF THE SILICON-ON-INSULATOR TYPE
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United States of America Patent
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Nov 2, 2017
app pub date -
Nov 28, 2016
filing date -
Apr 27, 2016
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Abstract
An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.
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