Static random access memory (SRAM) cell including fin-type transistor
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United States of America Patent
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Dec 11, 2018
Grant Date -
Nov 2, 2017
app pub date -
Jul 18, 2017
filing date -
Jan 19, 2015
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Abstract
The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.
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