Temperature compensated read assist circuit for a static random access memory (SRAM)
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United States of America Patent
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Apr 19, 2016
filing date -
Apr 19, 2016
priority date (Note) -
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Abstract
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.
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