READ DISCARDS IN A PROCESSOR SYSTEM WITH WRITE-BACK CACHES
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Apr 7, 2016
filing date -
Apr 7, 2016
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A system and method provide for a better way of managing a shared memory system. A multiprocessor system includes a first and second CPU, with each CPU having a private L1 cache. The system further includes a level 2 (L2) cache shared between the first CPU and the second CPU, and includes a memory coherency manager (CM) and an I/O device. The second CPU is configured to request ownership of a cache line in the L1 cache of the first CPU that is in a Modified state. Later, upon receiving a read discard command from the I/O device, the second CPU is configured to request the CM update the cache line from a Modified state to a Shared state.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully