EXCEPTION HANDLING IN PROCESSOR USING BRANCH DELAY SLOT INSTRUCTION SET ARCHITECTURE
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United States of America Patent
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Mar 24, 2016
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Mar 24, 2016
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A processor employs hardware to save the program counter value of the next instruction to be executed in a branch instruction when an exception occurs. This is the branch target address in the case where the exception occurs in the delay slot of a taken branch. The value is saved to a register when an exception occurs. The kernel code can then read the register to determine the address which it should return to after an exception. This eliminates the need to emulate the branch instruction and also eliminates the need to keep the kernel up to date with the knowledge of how to emulate all branches in an Instruction Set Architecture.
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