Multiplexer reduction for programmable logic devices
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United States of America Patent
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Jul 17, 2018
Grant Date -
Sep 21, 2017
app pub date -
Mar 17, 2016
filing date -
Sep 11, 2015
priority date (Note) -
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Abstract
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a method includes identifying a multiplexer in the design, identifying one or more irrelevant inputs for the multiplexer by, at least in part, decomposing the select logic into one or more select line binary decision diagrams corresponding to the one or more select lines, and generating a reduced multiplexer by eliminating the one or more irrelevant inputs from the multiplexer. The reduced multiplexer may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.
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