Hierarchical packing of syntax elements
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United States of America Patent
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Nov 17, 2020
Grant Date -
Sep 14, 2017
app pub date -
May 27, 2017
filing date -
Oct 6, 2006
priority date (Note) -
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Abstract
A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.
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