Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect structure
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Jan 30, 2017
filing date -
Mar 8, 2016
priority date (Note) -
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Abstract
An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.
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