Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 11, 2020
Grant Date -
Sep 14, 2017
app pub date -
May 25, 2017
filing date -
Mar 8, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 41.95 % this patent is cited more than
- 5 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Feb 11, 2028 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Feb 11, 2032 |
