Control of persistent memory via a computer bus
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United States of America Patent
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Sep 15, 2020
Grant Date -
Sep 7, 2017
app pub date -
Mar 2, 2016
filing date -
Mar 2, 2016
priority date (Note) -
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Abstract
A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.
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