METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
May 17, 2017
filing date -
Sep 4, 2015
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully