WEAR LEVELING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

Number of patents in Portfolio can not be more than 2000

United States of America Patent

SERIAL NO

15080564

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A wear leveling method, a memory control circuit unit and a memory storage device are provided. The method includes: selecting a first physical erasing unit from physical erasing units not stored with valid data according to erase counts, and selecting a second physical erasing unit having a valid data amount being less than a capacity of one physical erasing unit from the physical erasing units stored with the valid data. The method also includes: selecting a third physical erasing unit having the valid data amount being less than the capacity of one physical erasing unit from the physical erasing units storing valid data according to the erase counts. The method further includes: writing the valid data of the second physical erasing unit and at least part of the valid data of the third physical erasing unit into the first physical erasing unit.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
PHISON ELECTRONICS CORPNO 1 QUN YI RD JHUNAN MIAOLI 350

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Jyun-Kai Taoyuan City, TW 4 8

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation