Junctionless transistor based on vertically integrated gate-all-round multiple nanowire channels and method of manufacturing the same
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United States of America Patent
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May 26, 2020
Grant Date -
Aug 17, 2017
app pub date -
Feb 9, 2017
filing date -
Feb 16, 2016
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Abstract
Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.
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