SYSTEM AND METHOD FOR LAYOUT SIMPLIFICATION
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United States of America Patent
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Issued Date -
Aug 10, 2017
app pub date -
Feb 9, 2016
filing date -
Feb 9, 2016
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Abstract
A system and method is disclosed for verifying semiconductor circuit layouts. A resistor stick network model of the semiconductor circuit layout is generated from a low frequency extraction of the circuit. The resistor stick network then can be used to determine open or short in the circuit by comparing the pairwise terminal resistance of each circuit node thus eliminating open/short failures in the circuit.
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