Data protection for memory with built-in self-test
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United States of America Patent
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Jun 25, 2019
Grant Date -
Aug 3, 2017
app pub date -
Aug 31, 2016
filing date -
Feb 3, 2016
priority date (Note) -
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Abstract
Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.
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