LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 20, 2017
app pub date -
Aug 25, 2016
filing date -
Jan 19, 2016
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A latch circuit provided herein includes an input circuit including a PMOS transistor that is configured for input and enables a signal current to flow into the PMOS transistor; a first inverter comprising a first PMOS transistor, a first NMOS transistor, and a first node; a second inverter comprising a second PMOS transistor, a second NMOS transistor, and a second node. The signal current corresponds to a sense voltage from a sense amplifier. The first PMOS transistor and the first NMOS transistor are connected to each other through the first node, and the first node is connected to the input circuit. The second PMOS transistor and the second NMOS transistor are connected to each other through the second node. The first inverter and the second inverter are cascaded.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully