Dicing method for wafer-level packaging and semiconductor chip with dicing structure adapted for wafer-level packaging
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United States of America Patent
Stats
-
Mar 13, 2018
Issued Date -
N/A
app pub date -
May 21, 2015
filing date -
May 28, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a polyimide layer (8) spanning the trenches (7) is applied above the integrated circuits, a tape layer (14) is applied above the polyimide layer (8), and a layer portion of the substrate (1) is removed from the substrate side (17) opposite the tape layer (14), until the trenches (7) are opened and dicing of the substrate (1) is thus effected. The polyimide layer (8) is severed in sections (18) above the trenches (7) when the tape layer (14) is removed. The semiconductor chip is provided with a cover layer (11) laterally confining the polyimide layer (8) near the trenches (7), in particular for forming breaking delimitations (9).
First Claim
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International Classification(s)
- 2015 Application Filing Year
- H01L Class
- 25498 Applications Filed
- 22451 Patents Issued To-Date
- 88.06 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
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|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Sep 13, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 13, 2029 |
